/******************************************************************************
  * @file    PT32X005.h
  * @author  应用开发团队
  * @version V1.1.0
  * @date    2020/1/27
  * @brief
  *
  ******************************************************************************
  * @attention
  *
  *
  *****************************************************************************/


#ifndef PT32X005_H
#define PT32X005_H

#ifdef __cplusplus
 extern "C" {
#endif

#if defined (__CC_ARM)
#pragma anon_unions
#endif



#define __CM0_REV			0	/* Core Revision r0p0	*/
#define __MPU_PRESENT		0	/* do not provide MPU	*/
#define __NVIC_PRIO_BITS	2	/* uses 2 Bits for the Priority Levels  */
#define __Vendor_SysTickConfig	0	/* Set to 1 if different SysTick Config is used  */



/**
 *@brief Interrupt Number Definition
**/
typedef enum IRQn
{
	/************************ Cortex-M0 Processor Exceptions Numbers ************************/

	NMI_IRQn		= -14,	/* 2 Non Maskable Interrupt	*/
	HardFault_IRQn	= -13,	/* 3 Cortex-M0 Hard Fault Interrupt	*/
	SVCall_IRQn		= -5,	/* 11 Cortex-M0 SV Call Interrupt	*/
	PendSV_IRQn	= -2,	/* 14 Cortex-M0 Pend SV Interrupt	*/
	SysTick_IRQn	= -1,	/* 15 Cortex-M0 System Tick Interrupt	*/

	/************************  MCU Specific Interrupt Numbers ************************/

	PLLFAIL_IRQn	=  1 ,	/* PLLFAIL    Interrupt 	*/
	IFMC_IRQn		=  3 ,	/* IFMC       Interrupt 	*/
	EXTIA_IRQn		=  5 ,	/* EXTIA      Interrupt 	*/
	EXTIB_IRQn		=  6 ,	/* EXTIB      Interrupt 	*/
	EXTIC_IRQn		=  7,	/* EXTIC      Interrupt 	*/
	EXTID_IRQn		=  8,	/* EXTID      Interrupt 	*/
	ADC_IRQn		=  12,	/* ADC        Interrupt 	*/
	TIM1_IRQn		=  13,	/* TIM1       Interrupt 	*/
	TIM4_IRQn		=  15,	/* TIM4       Interrupt 	*/
	TIM3_IRQn		=  16,	/* TIME3      Interrupt 	*/
	TIM2_IRQn		=  17,	/* TIM2       Interrupt 	*/
	PVD_IRQn		=  20,	/* PVD        Interrupt 	*/
	I2C_IRQn		=  23,	/* I2C        Interrupt 	*/
	SPI_IRQn		=  25,	/* SPI        Interrupt 	*/
	UART0_IRQn		=  27,	/* UART0      Interrupt 	*/
	UART1_IRQn		=  28,	/* UART1      Interrupt 	*/

} IRQn_Type;


#include "core_cm0.h"
#include "PT32X005_Type.h"
#include <stdint.h>



/** @addtogroup Exported_types
  * @{
**/
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, RemapStatus, ProtectStatus;

typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))

#define wb(addr, value)     (*((u8  volatile *) (addr)) = value)
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
typedef enum {FALSE = 0, TRUE = !FALSE} bool;
/**
  * @}
**/

/**
 * @brief CRC结构体
**/
typedef struct
{
	__IO u32  CR;				/* Offset: 0x000 CRC 控制寄存器		(R/W) */
	__IO u32  SEED;			/* Offset: 0x004 CRC Seed Register 			(R/W) */
	__IO u32  POLY;			/* Offset: 0x008 CRC polynomial Register		(R/W) */
	__O  u32  DIN;			/* Offset: 0x00C CRC Data INPUT Register		(W)	  */
	__I  u32  DOUT;			/* Offset: 0x010 CRC Data OUTPUT Register	(R)	  */
} CRC_TypeDef;

/**
 * @brief 电源控制结构体
**/
typedef struct
{
	__IO u32  PVDR;			/* Offset: 0x000 VDD Low Voltage Detect Control Register 	 (R/W) */
	u32  RESERVED0[671102275];
	__IO u32  SCR;	  	/* Addr:0xE000_ED10 系统控制寄存器	(R/W) */
} PWR_TypeDef;

/**
  * @brief  RCC
**/
typedef struct
{
	__IO u32  HCR;			/* Offset: 0x000 48MHZ IOSC Control Register 							  (R/W) */
	__IO u32  LCR;			/* Offset: 0x004 32KHZ IOSC Control Register 							  (R/W) */
	__IO u32  PCR;   		/* Offset: 0x008 Frequency doubling module control register (R/W) */
	u32  RESERVED0[2];
	__IO u32  MCOR;			/* Offset: 0x014 MCO Frequency Division Control Register 		(R/W) */
	u32  RESERVED1[30201];
	__IO u32  CFGR;			/* Addr:	 0x4001_F00C System Clock Selection Register 			(R/W) */
	__IO u32  RSR;			/* Addr:	 0x4001_F010 Reset Information Register 					(R/W) */
	__O  u32  HSFRR;		/* Addr: 	 0x4001_F014 Reset Information Register						(W) 	*/
	__IO u32  RCR;			/* Addr: 	 0x4001_F018 RSTEN Ccontrol Register 							(R/W) */
} RCC_TypeDef;

/**
  * @brief General Purpose IO
**/
typedef struct
{
	__IO u32  DR;     	/* Offset: 0x000 DATA Register 														 (R/W) */
	__IO u32  RESERVED0;
	__IO u32  OES;			/* Offset: 0x008 Output Enable Set Register  							 (R/W) */
	__O  u32  OEC; 			/* Offset: 0x00C Output Enable Clear Register 						 (W) 	*/
	u32  RESERVED1[12];
	__IO u32  PUS;			/* Offset: 0x040 Pull Up Set Register  										 (R/W) */
	__O  u32  PUC;			/* Offset: 0x044 Pull Up Clear Register  									 (W) 	*/
	__IO u32  PDS;			/* Offset: 0x048 Pull Down Set Register  									 (R/W) */
	__O  u32  PDC;			/* Offset: 0x04C Pull Down Clear Register  								 (W) 	*/
	__IO u32  ODS;			/* Offset: 0x050 Open Drain Set Register  								 (R/W) */
	__O  u32  ODC;			/* Offset: 0x054 Open Drain Clear Register  							 (W) 	*/
	u32  RESERVED2[6];
	__IO u32  CSS;			/* Offset: 0x070 Sthmidt set Register 										 (R/W) */
	__O  u32  CSC;			/* Offset: 0x074 Sthmidt Clear Register 									 (W)	  */
	u32  RESERVED3[226];
	__O  u32 MASKL[256];/* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (W) 	*/
	__O  u32 MASKH[256];/* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (W) 	*/
} GPIO_TypeDef;

/**
 * @brief AFIO
**/
typedef struct
{
  __IO u32  AFS0;	  	/* Offset: 0x000 Alternate Function Set Register0 		(R/W) */
	__IO u32  AFS1;    	/* Offset: 0x004 Alternate Function Set Register1 		(R/W) */
	__O  u32  AFC;    	/* Offset: 0x008 Alternate Function Clear Register0  	(W) 	*/
	u32 RESERVED0[15];
	__IO u32  ANAS;			/* Offset: 0x048 Analog function Set Register  				(R/W) */
	__O  u32  ANAC;			/* Offset: 0x04C Analog function Clear Register  			(W) 	*/
} AFIO_TypeDef;

/**
 * @brief EXTI
**/
typedef struct
{
	__IO u32  IES;     	/* Offset: 0x000 Interrupt Enable Set Register  	 (R/W) */
	__O  u32  IEC;    	/* Offset: 0x004 Interrupt Enable Clear Register   (W)   */
	__IO u32  ITS;      /* Offset: 0x008 Interrupt Type Set Register0  		 (R/W) */
	__O  u32  ITC;      /* Offset: 0x00C Interrupt Type Clear Register0    (W)   */
	__IO u32  ITDS;	    /* Offset: 0x010 Interrupt Type Set Register1  		 (R/W) */
	__O  u32  ITDC;	    /* Offset: 0x014 Interrupt Type Clear Register1  	 (W)	  */
	__IO u32  PTS;      /* Offset: 0x018 Interrupt Polarity Set Register   (R/W) */
	__O  u32  PTC;   	  /* Offset: 0x01C Interrupt Polarity Clear Register (W)   */
	__IO u32  IF;	     	/* Offset: 0x020 Interrupt Status Register  			 (R/W) */
} EXTI_TypeDef;

/**
  * @brief  Analog to Digital Converter
**/
typedef struct
{
	__IO u32 CR;     		/* Offset: 0x000 ADC Control register 		 (R/W) */
	__I  u32 SR;    		/* Offset: 0x004 ADC Status Register  		 (R) */
	__I  u32 DR;    		/* Offset: 0x008 ADC data register 				 (R) 	 */
	__IO u32 SAMPLE;		/* Offset: 0x00C ADC SAMPLE TIMER register (R/W) */
} ADC_TypeDef;

/**
  * @brief TIM1
**/
typedef struct
{
	__IO u32 SR;        /* offset: 0x000 Interrupt status Register   (R/W) */
	__IO u32 CR1;       /* offset: 0x004 Control Register            (R/W) */
	__IO u32 ITARR;     /* offset: 0x008 Interrupt Repeat Timers     (R/W) */
	__I  u32 ITCNT;     /* offset: 0x00C Interrupt Repeat Timers CNT (R)   */
	__IO u32 PSC;       /* offset: 0x010 Prescale Register           (R/W) */
	u32 RESERVED0;
	__IO u32 CNT;       /* offset: 0x018 Timer Counter Register      (R/W) */
	__IO u32 CR2;       /* offset: 0x01C Match Control Register      (R/W) */
	__IO u32 ARR;       /* offset: 0x020 Match Value Register0       (R/W) */
	__IO u32 OCR1;      /* offset: 0x024 Match Value Register1       (R/W) */
	__IO u32 OCR2;      /* offset: 0x028 Match Value Register2       (R/W) */
	__IO u32 OCR3;      /* offset: 0x02C Match Value Register3       (R/W) */
	__IO u32 OCR4;      /* offset: 0x030 Match Value Register4       (R/W) */
	__IO u32 CAPR;      /* offset: 0x034 Capture Control Register    (R/W) */
	__I  u32 ICR1;      /* offset: 0x038 Capture Value Register1     (R)   */
	__I  u32 ICR2;      /* offset: 0x03C Capture Value Register2     (R)   */
	__I  u32 ICR3;      /* offset: 0x040 Capture Value Register3     (R)   */
	__I  u32 ICR4;      /* offset: 0x044 Capture Value Register4     (R)   */
	__IO u32 OCMR;      /* offset: 0x048 Compare Output Register     (R/W) */
	__IO u32 DT;        /* offset: 0x04C Death Time Register         (R/W) */
} TIM1_TypeDef;

/**
  * @brief TIMx
**/
typedef struct
{
	__IO u32 SR;        /* offset: 0x000 Interrupt status Register   (R/W) */
	__IO u32 CR1;       /* offset: 0x004 Control Register            (R/W) */
	__IO u32 PSC;       /* offset: 0x008 Prescale Register           (R/W) */
	u32 RESERVED0;
	__IO u32 CNT;       /* offset: 0x010 Timer Counter Register      (R/W) */
	__IO u32 CR2;       /* offset: 0x014 Match Control Register      (R/W) */
	__IO u32 ARR;       /* offset: 0x018 Match Value Register0       (R/W) */
} TIMx_TypeDef;

/**
  * @brief IWDG
**/
typedef struct
{
	__IO u32 RLR;		/* offset: 0x000 IWDG Reload register    (R/W) */
	__I  u32 CNT; 	  	/* offset: 0x004 IWDG COUNT register     (R/W) */
	__IO u32 CR;    		/* offset: 0x008 IWDG Control register   (R/W) */
	__O  u32 KR;  	  	/* offset: 0x00C IWDG Interrupt clear    (W)   */
	__I  u32 SR;   		/* offset: 0x010 IWDG Window register    (R)   */
	u32 RESERVED0[251];
	__IO u32 LOCK;   		/* offset: 0x400 IWDG Window register    (R/W) */
} IWDG_TypeDef;

/**
  * @brief Serial Peripheral Interface
**/
typedef struct
{
	__IO u32 CR1;	/* offset: 0x000 SPI Control register 1                 (R/W) */
	__IO u32 CR2;       /* offset: 0x004 SPI Control register 2                 (R/W) */
	__IO u32 DR;        /* offset: 0x008 SPI data register                      (R/W) */
	__I  u32 SR1;       /* offset: 0x00C SPI Status register                    (R)   */
	__IO u32 BR; 	     	/* offset: 0x010 SPI Clock prescaler register           (R/W) */
	__IO u32 IE;        /* offset: 0x014 SPI Interrupt ENABLE register          (R/W) */
	__I  u32 SR2;       /* offset: 0x018 SPI Interrupt Raw Int Status register  (R)   */
	u32 RESERVED0;
	__O  u32 IFC;       /* offset: 0x020 SPI Interrupt Clear Register register  (W)   */
	u32 RESERVED1;
	__IO u32 CSS;       /* offset: 0x028 SPI Chip-Select Control register       (R/W) */
} SPI_TypeDef;

/**
  * @brief Inter-integrated Circuit Interface
**/
typedef struct
{
	__IO u32 CR;		    /* offset: 0x000 I2C Control Set register     (R/W) */
	__I  u32 SR; 		    /* offset: 0x004 I2C status register          (R)   */
	__IO u32 DR;     	  /* offset: 0x008 I2C data register            (R/W) */
	__IO u32 OAR;	      /* offset: 0x00C I2C Own address register     (R/W) */
	__IO u32 RESERVED0;
	__IO u32 RESERVED1;
	__O  u32 CCR; 		  /* offset: 0x018 I2C Control Reset register 2 (W)   */
} I2C_TypeDef;

/**
  * @brief UART
**/
typedef struct
{
	__IO u32 DR;     		/* Offset: 0x000 Buffer Register 						(R/W) */
	__IO u32 CR;		    /* Offset: 0x004 Control Register						(R/W) */
	__IO u32 BRR;     	/* Offset: 0x008 Baud Rate Register					(R/W) */
	__IO u32 IE;    	  /* Offset: 0x00C Interrupt Enable Register	(R/W) */
	__IO u32 SR;     		/* Offset: 0x010 Status Register						(R/W) */
	u32 RESERVED0;
	u32 RESERVED1;
	__O  u32 TXFR; 	  	/* Offset: 0x01C TX Buffer Reset Register  	(W)  */
	__O  u32 RXFR;   		/* Offset: 0x020 RX Buffer Reset Register  	(W)  */
	u32 RESERVED2;
	__IO u32 IRC;				/* Offset: 0x028 Infra-red Control Register (R/W) */
	__IO u32 IRDC;		  /* Offset: 0x02C IR TX PWM Control Register (R/W) */
} UART_TypeDef;

/**
  * @brief IFMC
**/
typedef struct
{
	__IO u32 CR; 	     	/* Offset: 0x000 Flash Command Register              (R/W) */
	__IO u32 SR;   	    /* Offset: 0x004 Flash Interrupt status Register     (R/W) */
	__IO u32 IE;  	    /* Offset: 0x008 Flash Interrupt Enable Register     (R/W) */
	__IO u32 AR;    	  /* Offset: 0x00C Flash Address Register 						 (R/W) */
	__IO u32 DR;  	    /* Offset: 0x010 Flash Programming Data Register0  	 (R/W) */
	u32  RESERVED0[5];
	__IO u32 PSC;  	    /* Offset: 0x028 Flash Erase Clock Division Register (R/W) */
	u32 RESERVED01[31733];
	__IO u32 BSR;       /* Addr: 	 0x4001_F000 Remap Control Register        (R/W) */
	u32 RESERVED02[8];
	__I u32 RPT;        /* Addr:   0x4001_F024 FLash Protect Status Register (R)   */
} IFMC_TypeDef;

/**
  * @brief ID
**/
typedef struct
{
	__I  u32  UDID;     /* Offset: 0x000 Customer ID information Register (R) */
	u32 RESERVED0[3];
	__I  u32  UID1;   	/* Offset: 0x010 UID information Register         (R) */
	__I  u32  UID2;   	/* Offset: 0x014 UID information Register 				(R) */
	__I  u32  UID3;   	/* Offset: 0x018 UID information Register 				(R) */
	__I  u32  CID;      /* Offset: 0x01C CID information Register 				(R) */

} ID_TypeDef;


#define FLASH_BASE	(0x00000000) 			/* FLASH base address in the alias region */
#define SRAM_BASE	(0x20000000) 			/* SRAM base address in the alias region */
#define APB_BASE	(0x40000000)
#define AHB_BASE	(0x48000000)

/* AHB peripherals */
#define GPIOA_BASE	(AHB_BASE + 0x00000000)
#define GPIOB_BASE	(AHB_BASE + 0x00001000)
#define GPIOC_BASE	(AHB_BASE + 0x00002000)
#define GPIOD_BASE	(AHB_BASE + 0x00003000)

#define EXTIA_BASE	(AHB_BASE + 0x0000001C)
#define EXTIB_BASE	(AHB_BASE + 0x0000101C)
#define EXTIC_BASE	(AHB_BASE + 0x0000201C)
#define EXTID_BASE	(AHB_BASE + 0x0000301C)

#define AFIOA_BASE	(AHB_BASE + 0x00000010)
#define AFIOB_BASE	(AHB_BASE + 0x00001010)
#define AFIOC_BASE	(AHB_BASE + 0x00002010)
#define AFIOD_BASE	(AHB_BASE + 0x00003010)

/* APB peripherals */
#define CRC_BASE	(APB_BASE + 0x00003C00)

#define PWR_BASE	(APB_BASE + 0x00001800)

#define RCC_BASE	(APB_BASE + 0x00001810)

#define ADC_BASE	(APB_BASE + 0x00012400)

#define TIMER1_BASE	(APB_BASE + 0x00012C00)
#define TIMER2_BASE	(APB_BASE + 0x00001000)
#define TIMER3_BASE	(APB_BASE + 0x00001400)
#define TIMER4_BASE	(APB_BASE + 0x00001C00)

#define IWDG_BASE	(APB_BASE + 0x00003000)

#define SPI_BASE		(APB_BASE + 0x00013000)

#define I2C_BASE		(APB_BASE + 0x00005400)

#define UART0_BASE	(APB_BASE + 0x00004400)
#define UART1_BASE	(APB_BASE + 0x00013800)

#define IFMC_BASE	(APB_BASE + 0x00000000)

#define ID_BASE		(APB_BASE + 0x0001F020)



#define SYSCTRL_BASE	(APB_BASE + 0x0001F000)


/**
  * @}
**/


/** @addtogroup Peripheral_declaration
  * @{
**/

#define GPIOA	((GPIO_TypeDef     *) GPIOA_BASE )
#define GPIOB	((GPIO_TypeDef     *) GPIOB_BASE )
#define GPIOC	((GPIO_TypeDef     *) GPIOC_BASE )
#define GPIOD	((GPIO_TypeDef     *) GPIOD_BASE )

#define EXTIA	((EXTI_TypeDef     *) EXTIA_BASE )
#define EXTIB	((EXTI_TypeDef     *) EXTIB_BASE )
#define EXTIC	((EXTI_TypeDef     *) EXTIC_BASE )
#define EXTID	((EXTI_TypeDef     *) EXTID_BASE )

#define UART0	((UART_TypeDef     *) UART0_BASE )
#define UART1	((UART_TypeDef     *) UART1_BASE )

#define IFMC		((IFMC_TypeDef     *) IFMC_BASE )
#define ADC		((ADC_TypeDef      *) ADC_BASE )

#define AFIOA	((AFIO_TypeDef     *)AFIOA_BASE)
#define AFIOB	((AFIO_TypeDef     *)AFIOB_BASE)
#define AFIOC	((AFIO_TypeDef     *)AFIOC_BASE)
#define AFIOD	((AFIO_TypeDef     *)AFIOD_BASE)

#define I2C		((I2C_TypeDef      *) I2C_BASE )

#define SPI		((SPI_TypeDef      *) SPI_BASE )

#define TIM1		((TIM1_TypeDef     *) TIMER1_BASE )
#define TIM2		((TIMx_TypeDef     *) TIMER2_BASE )
#define TIM3		((TIMx_TypeDef     *) TIMER3_BASE )
#define TIM4		((TIMx_TypeDef     *) TIMER4_BASE )

#define ID		((ID_TypeDef       *) ID_BASE )
#define RCC		((RCC_TypeDef      *) RCC_BASE )

#define CRC		((CRC_TypeDef      *) CRC_BASE )
#define PWR		((PWR_TypeDef      *) PWR_BASE )
#define IWDG	((IWDG_TypeDef     *) IWDG_BASE )




/******************************************************************************/
/*                                                                            */
/*                                  RCC                                  */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for RCC_HCR register  ******************/
#define RCC_HCR_HSIEN                ((u32)0x00000001)        /*  */
/********************  Bits definition for RCC_LCR register  ******************/
#define RCC_LCR_LSIEN                ((u32)0x00000001)        /*  */
/********************  Bits definition for RCC_PCR register  ******************/
#define RCC_PCR_PLLEN                ((u32)0x00000001)        /*  */
/********************  Bits definition for RCC_MCOR register  ******************/
#define RCC_MCOR_COPRE               ((u32)0x00000007)        /*  */
#define RCC_MCOR_COPRE_1DIV          ((u32)0x00000000)        /*  */
#define RCC_MCOR_COPRE_2DIV          ((u32)0x00000001)        /*  */
#define RCC_MCOR_COPRE_4DIV          ((u32)0x00000002)        /*  */
#define RCC_MCOR_COPRE_8DIV          ((u32)0x00000003)        /*  */
#define RCC_MCOR_COPRE_16DIV         ((u32)0x00000004)        /*  */
#define RCC_MCOR_COSRC               ((u32)0x00000030)        /*  */
#define RCC_MCOR_COSRC_HSI           ((u32)0x00000000)        /*  */
#define RCC_MCOR_COSRC_PLL           ((u32)0x00000010)        /*  */
#define RCC_MCOR_COSRC_LSI           ((u32)0x00000020)        /*  */
#define RCC_MCOR_COSRC_SYSCLK        ((u32)0x00000030)        /*  */
/********************  Bits definition for RCC_CFGR register  ******************/
#define RCC_CFGR_SCW			((u32)0x00000003)        /*  */
#define RCC_CFGR_SCW_HSI		((u32)0x00000000)        /*  */
#define RCC_CFGR_SCW_PLL		((u32)0x00000002)        /*  */
#define RCC_CFGR_SCW_LSI		((u32)0x00000003)        /*  */
#define RCC_CFGR_PLLSRC			((u32)0x00000004)        /*  */
#define RCC_CFGR_PLLSRC_HSI	((u32)0x00000000)        /*  */
#define RCC_CFGR_PLLSRC_LSI	((u32)0x00000004)        /*  */
#define RCC_CFGR_HPRE			((u32)0x000001F0)        /*  */
#define RCC_CFGR_PLLF			((u32)0x00008000)        /*  */
#define RCC_CFGR_WKDL			((u32)0x00030000)        /*  */
#define RCC_CFGR_WKSK			((u32)0x00100000)        /*  */
#define RCC_CFGR_PPRE			((u32)0x1F000000)        /*  */
/********************  Bits definition for RCC_RSR register  ******************/
#define RCC_RSR_SFR                  ((u32)0x00000001)        /*  */
#define RCC_RSR_IWDGR                ((u32)0x00000002)        /*  */
#define RCC_RSR_PLLR                 ((u32)0x00000020)	/*  */
#define RCC_RSR_POR                  ((u32)0x00000040)        /*  */
#define RCC_RSR_PINR                 ((u32)0x00000080)        /*  */
#define RCC_RSR_PVDR                 ((u32)0x00000100)        /*  */
/********************  Bits definition for RCC_HSFRR register  ******************/
#define RCC_HSFRR_CTRL               ((u32)0x0000FFFF)        /*  */
/********************  Bits definition for RCC_RCR register  ******************/
#define RCC_RCR_PREN                 ((u32)0x00000020)        /*  */
#define RCC_RCR_PDRE                 ((u32)0x00000100)        /*  */
#define RCC_RCR_HREN                 ((u32)0x00000400)        /*  */

/******************************************************************************/
/*                                                                            */
/*                                  ID                                 */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for ID_UDID register  ******************/
#define ID_UDID_DATA                   ((u32)0xFFFFFFFF)        /*  */
/********************  Bits definition for ID_UID1_DATA register  ******************/
#define ID_UID1_DATA                         ((u32)0xFFFFFFFF)        /*  */
/********************  Bits definition for ID_UID2_DATAregister  ******************/
#define ID_UID2_DATA                        ((u32)0xFFFFFFFF)        /*  */
/********************  Bits definition for ID_UID3_DATA register  ******************/
#define ID_UID3_DATA                         ((u32)0xFFFFFFFF)        /*  */
/********************  Bits definition for SYSCON_CID register  ******************/
#define ID_CID_F_SIZE                     ((u32)0x00000001)        /*  */
#define ID_CID_S_SIZE                      ((u32)0x00000010)        /*  */
#define ID_CID_B_SIZE                      ((u32)0x00000300)        /*  */
#define ID_CID_C_TYPE                           ((u32)0x0000F000)
#define ID_CID_RES                          ((u32)0xFFFF0000)      /*  */


/******************************************************************************/
/*                                                                            */
/*                          PWR                    */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for PWR_PVDR  register  ******************/
#define PWR_PVDR_PVDE		((u32)0x00000001)        /*  */

#define PWR_PVDR_PLS		((u32)0x0000000E)        /*  */
#define PWR_PLS_Level0		((u32)0x00000000)        /*  */
#define PWR_PLS_Level1		((u32)0x00000002)        /*  */
#define PWR_PLS_Level2		((u32)0x00000004)        /*  */
#define PWR_PLS_Level3		((u32)0x00000006)        /*  */
#define PWR_PLS_Level4		((u32)0x00000008)        /*  */


/******************************************************************************/
/*                                                                            */
/*                       General Purpose IOs (GPIO)                           */
/*                                                                            */
/******************************************************************************/

#define GPIO_Pin_0                 ((u16)0x0001)  /* Pin 0 selected    */
#define GPIO_Pin_1                 ((u16)0x0002)  /* Pin 1 selected    */
#define GPIO_Pin_2                 ((u16)0x0004)  /* Pin 2 selected    */
#define GPIO_Pin_3                 ((u16)0x0008)  /* Pin 3 selected    */
#define GPIO_Pin_4                 ((u16)0x0010)  /* Pin 4 selected    */
#define GPIO_Pin_5                 ((u16)0x0020)  /* Pin 5 selected    */
#define GPIO_Pin_6                 ((u16)0x0040)  /* Pin 6 selected    */
#define GPIO_Pin_7                 ((u16)0x0080)  /* Pin 7 selected    */
#define GPIO_Pin_8                 ((u16)0x0100)  /* Pin 8 selected    */
#define GPIO_Pin_9                 ((u16)0x0200)  /* Pin 9 selected    */
#define GPIO_Pin_10                ((u16)0x0400)  /* Pin 10 selected   */
#define GPIO_Pin_11                ((u16)0x0800)  /* Pin 11 selected   */
#define GPIO_Pin_12                ((u16)0x1000)  /* Pin 12 selected   */
#define GPIO_Pin_13                ((u16)0x2000)  /* Pin 13 selected   */
#define GPIO_Pin_14                ((u16)0x4000)  /* Pin 14 selected   */
#define GPIO_Pin_15                ((u16)0x8000)  /* Pin 15 selected   */
#define GPIO_Pin_All               ((u16)0xFFFF)  /* All pins selected */

/******************************************************************************/
/*                                                                            */
/*                                      AFIO                                  */
/*                                                                            */
/******************************************************************************/
#define AFIO_Pin_0                 ((u16)0x0001)  /* Pin 0 selected    */
#define AFIO_Pin_1                 ((u16)0x0002)  /* Pin 1 selected    */
#define AFIO_Pin_2                 ((u16)0x0004)  /* Pin 2 selected    */
#define AFIO_Pin_3                 ((u16)0x0008)  /* Pin 3 selected    */
#define AFIO_Pin_4                 ((u16)0x0010)  /* Pin 4 selected    */
#define AFIO_Pin_5                 ((u16)0x0020)  /* Pin 5 selected    */
#define AFIO_Pin_6                 ((u16)0x0040)  /* Pin 6 selected    */
#define AFIO_Pin_7                 ((u16)0x0080)  /* Pin 7 selected    */
#define AFIO_Pin_8                 ((u16)0x0100)  /* Pin 8 selected    */
#define AFIO_Pin_9                 ((u16)0x0200)  /* Pin 9 selected    */
#define AFIO_Pin_10                ((u16)0x0400)  /* Pin 10 selected   */
#define AFIO_Pin_11                ((u16)0x0800)  /* Pin 11 selected   */
#define AFIO_Pin_12                ((u16)0x1000)  /* Pin 12 selected   */
#define AFIO_Pin_13                ((u16)0x2000)  /* Pin 13 selected   */
#define AFIO_Pin_14                ((u16)0x4000)  /* Pin 14 selected   */
#define AFIO_Pin_15                ((u16)0x8000)  /* Pin 15 selected   */
#define AFIO_Pin_All               ((u16)0xFFFF)  /* All pins selected */

#define AFIO_AF_None		 ((u8)0x00)
#define AFIO_AF_0            ((u8)0x01)	/** @brief  AF 0 selection **/
#define AFIO_AF_1            ((u8)0x02)	/** @brief  AF 1 selection **/
#define AFIO_AF_2            ((u8)0x03)	/**@brief   AF 2 selection **/
#define AFIO_AF_3            ((u8)0x04)	/** @brief  AF 3 selection **/
#define AFIO_AF_4            ((u8)0x05)	/** @brief  AF 4 selection **/
#define AFIO_AF_5            ((u8)0x06)	/** @brief  AF 5 selection **/
#define AFIO_AF_6            ((u8)0x07)	/** @brief  AF 6 selection **/

/****************** Bit definition for AFIO_AFS0 register  ********************/
#define AFIO_AFS0_IO0            ((u32)0x0000000F)
#define AFIO_AFS0_IO1            ((u32)0x000000F0)
#define AFIO_AFS0_IO2            ((u32)0x00000F00)
#define AFIO_AFS0_IO3            ((u32)0x0000F000)
#define AFIO_AFS0_IO4            ((u32)0x000F0000)
#define AFIO_AFS0_IO5            ((u32)0x00F00000)
#define AFIO_AFS0_IO6            ((u32)0x0F000000)
#define AFIO_AFS0_IO7            ((u32)0xF0000000)
/****************** Bit definition for AFIO_AFS1 register  ********************/
#define AFIO_AFS1_IO8             ((u32)0x0000000F)
#define AFIO_AFS1_IO9             ((u32)0x000000F0)
#define AFIO_AFS1_IO10            ((u32)0x00000F00)
#define AFIO_AFS1_IO11            ((u32)0x0000F000)
#define AFIO_AFS1_IO12            ((u32)0x000F0000)
#define AFIO_AFS1_IO13            ((u32)0x00F00000)
#define AFIO_AFS1_IO14            ((u32)0x0F000000)
#define AFIO_AFS1_IO15            ((u32)0xF0000000)
/*******************  Bit definition for AFIO_AFC register  *******************/
#define AFIO_AFC_BIT0                        ((u16)0x0001)                 /* Port alternate function bit reset, bit 0 */
#define AFIO_AFC_BIT1                        ((u16)0x0002)                 /* Port alternate function bit reset, bit 1 */
#define AFIO_AFC_BIT2                        ((u16)0x0004)                 /* Port alternate function bit reset, bit 2 */
#define AFIO_AFC_BIT3                        ((u16)0x0008)                 /* Port alternate function bit reset, bit 3 */
#define AFIO_AFC_BIT4                        ((u16)0x0010)                 /* Port alternate function bit reset, bit 4 */
#define AFIO_AFC_BIT5                        ((u16)0x0020)                 /* Port alternate function bit reset, bit 5 */
#define AFIO_AFC_BIT6                        ((u16)0x0040)                 /* Port alternate function bit reset, bit 6 */
#define AFIO_AFC_BIT7                        ((u16)0x0080)                 /* Port alternate function bit reset, bit 7 */
#define AFIO_AFC_BIT8                        ((u16)0x0100)                 /* Port alternate function bit reset, bit 8 */
#define AFIO_AFC_BIT9                        ((u16)0x0200)                 /* Port alternate function bit reset, bit 9 */
#define AFIO_AFC_BIT10                       ((u16)0x0400)                 /* Port alternate function bit reset, bit 10 */
#define AFIO_AFC_BIT11                       ((u16)0x0800)                 /* Port alternate function bit reset, bit 11*/
#define AFIO_AFC_BIT12                       ((u16)0x1000)                 /* Port alternate function bit reset, bit 12*/
#define AFIO_AFC_BIT13                       ((u16)0x2000)                 /* Port alternate function bit reset, bit 13*/
#define AFIO_AFC_BIT14                       ((u16)0x4000)                 /* Port alternate function bit reset, bit 14*/
#define AFIO_AFC_BIT15                       ((u16)0x8000)                 /* Port alternate function bit reset, bit 15*/
/*******************  Bit definition for AFIO_ANAS register  *******************/
#define AFIO_ANAS_BIT0                        ((u16)0x0001)               /* Port analog function bit set, bit 0 */
#define AFIO_ANAS_BIT1                        ((u16)0x0002)               /* Port analog function bit set, bit 1 */
#define AFIO_ANAS_BIT2                        ((u16)0x0004)               /* Port analog function bit set, bit 2 */
#define AFIO_ANAS_BIT3                        ((u16)0x0008)               /* Port analog function bit set, bit 3 */
#define AFIO_ANAS_BIT4                        ((u16)0x0010)               /* Port analog function bit set, bit 4 */
#define AFIO_ANAS_BIT5                        ((u16)0x0020)               /* Port analog function bit set, bit 5 */
#define AFIO_ANAS_BIT6                        ((u16)0x0040)               /* Port analog function bit set, bit 6 */
#define AFIO_ANAS_BIT7                        ((u16)0x0080)               /* Port analog function bit set, bit 7 */
#define AFIO_ANAS_BIT8                        ((u16)0x0100)               /* Port analog function bit set, bit 8 */
#define AFIO_ANAS_BIT9                        ((u16)0x0200)               /* Port analog function bit set, bit 9 */
#define AFIO_ANAS_BIT10                       ((u16)0x0400)               /* Port analog function bit set, bit 10 */
#define AFIO_ANAS_BIT11                       ((u16)0x0800)               /* Port analog function bit set, bit 11*/
#define AFIO_ANAS_BIT12                       ((u16)0x1000)               /* Port analog function bit set, bit 12*/
#define AFIO_ANAS_BIT13                       ((u16)0x2000)               /* Port analog function bit set, bit 13*/
#define AFIO_ANAS_BIT14                       ((u16)0x4000)               /* Port analog function bit set, bit 14*/
#define AFIO_ANAS_BIT15                       ((u16)0x8000)               /* Port analog function bit set, bit 15*/
/*******************  Bit definition for AFIO_ANAC register  *******************/
#define AFIO_ANAC_BIT0                        ((u16)0x0001)               /* Port analog function bit reset, bit 0 */
#define AFIO_ANAC_BIT1                        ((u16)0x0002)               /* Port analog function bit reset, bit 1 */
#define AFIO_ANAC_BIT2                        ((u16)0x0004)               /* Port analog function bit reset, bit 2 */
#define AFIO_ANAC_BIT3                        ((u16)0x0008)               /* Port analog function bit reset, bit 3 */
#define AFIO_ANAC_BIT4                        ((u16)0x0010)               /* Port analog function bit reset, bit 4 */
#define AFIO_ANAC_BIT5                        ((u16)0x0020)               /* Port analog function bit reset, bit 5 */
#define AFIO_ANAC_BIT6                        ((u16)0x0040)               /* Port analog function bit reset, bit 6 */
#define AFIO_ANAC_BIT7                        ((u16)0x0080)               /* Port analog function bit reset, bit 7 */
#define AFIO_ANAC_BIT8                        ((u16)0x0100)               /* Port analog function bit reset, bit 8 */
#define AFIO_ANAC_BIT9                        ((u16)0x0200)               /* Port analog function bit reset, bit 9 */
#define AFIO_ANAC_BIT10                       ((u16)0x0400)               /* Port analog function bit reset, bit 10*/
#define AFIO_ANAC_BIT11                       ((u16)0x0800)               /* Port analog function bit reset, bit 11*/
#define AFIO_ANAC_BIT12                       ((u16)0x1000)               /* Port analog function bit reset, bit 12*/
#define AFIO_ANAC_BIT13                       ((u16)0x2000)               /* Port analog function bit reset, bit 13*/
#define AFIO_ANAC_BIT14                       ((u16)0x4000)               /* Port analog function bit reset, bit 14*/
#define AFIO_ANAC_BIT15                       ((u16)0x8000)               /* Port analog function bit reset, bit 15*/


/******************************************************************************/
/*                                                                            */
/*                                     EXTI                                   */
/*                                                                            */
/******************************************************************************/
#define EXTI_Pin_0		((u16)0x0001)		/* Pin 0 selected    */
#define EXTI_Pin_1		((u16)0x0002)		/* Pin 1 selected    */
#define EXTI_Pin_2		((u16)0x0004)		/* Pin 2 selected    */
#define EXTI_Pin_3		((u16)0x0008)		/* Pin 3 selected    */
#define EXTI_Pin_4		((u16)0x0010)		/* Pin 4 selected    */
#define EXTI_Pin_5		((u16)0x0020)		/* Pin 5 selected    */
#define EXTI_Pin_6		((u16)0x0040)		/* Pin 6 selected    */
#define EXTI_Pin_7		((u16)0x0080)		/* Pin 7 selected    */
#define EXTI_Pin_8		((u16)0x0100)		/* Pin 8 selected    */
#define EXTI_Pin_9		((u16)0x0200)		/* Pin 9 selected    */
#define EXTI_Pin_10		((u16)0x0400)		/* Pin 10 selected   */
#define EXTI_Pin_11		((u16)0x0800)		/* Pin 11 selected   */
#define EXTI_Pin_12		((u16)0x1000)		/* Pin 12 selected   */
#define EXTI_Pin_13		((u16)0x2000)		/* Pin 13 selected   */
#define EXTI_Pin_14		((u16)0x4000)		/* Pin 14 selected   */
#define EXTI_Pin_15		((u16)0x8000)		/* Pin 15 selected   */
#define EXTI_Pin_All	((u16)0xFFFF)		/* All pins selected */

#define EXTI_IT_0		((u16)0x0001)		/* Port interrupt selected 0 */
#define EXTI_IT_1		((u16)0x0002)		/* Port interrupt selected 1 */
#define EXTI_IT_2		((u16)0x0004)		/* Port interrupt selected 2 */
#define EXTI_IT_3		((u16)0x0008)		/* Port interrupt selected 3 */
#define EXTI_IT_4		((u16)0x0010)		/* Port interrupt selected 4 */
#define EXTI_IT_5		((u16)0x0020)		/* Port interrupt selected 5 */
#define EXTI_IT_6		((u16)0x0040)		/* Port interrupt selected 6 > */
#define EXTI_IT_7		((u16)0x0080)		/* Port interrupt selected 7 */
#define EXTI_IT_8		((u16)0x0100)		/* Port interrupt selected 8 */
#define EXTI_IT_9		((u16)0x0200)		/* Port interrupt selected 9 > */
#define EXTI_IT_10		((u16)0x0400)		/* Port interrupt selected 10 > */
#define EXTI_IT_11		((u16)0x0800)		/* Port interrupt selected 11 */
#define EXTI_IT_12		((u16)0x1000)		/* Port interrupt selected 12 */
#define EXTI_IT_13		((u16)0x2000)		/* Port interrupt selected 13 */
#define EXTI_IT_14		((u16)0x4000)		/* Port interrupt selected 14 */
#define EXTI_IT_15		((u16)0x8000)		/* Port interrupt selected 15 */
#define EXTI_IT_All		((u16)0xFFFF)		/* Port interrupt selected All */


/******************************************************************************/
/*                                                                            */
/*                      IFMC Registers                                       */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for IFMC_CR register  ******************/
#define  IFMC_CR_START			((u32)0x00000001)         /* 开始IFMC操作 */
#define  IFMC_CR_CMD			((u32)0x00000006)         /*IFMC操作命令  */
#define  IFMC_CR_CMD_PERA		((u32)0x00000002)         /* FLASH操作命令块擦除 */
#define  IFMC_CR_CMD_MERA		((u32)0x00000004)         /* FLASH操作命令主代码区擦除 */

#define  IFMC_CR_WAIT			((u32)0x00000020)   /* IFMC 取指令等待周期*/
#define  IFMC_WAIT_0			((u32)0x00000000)	/* IFMC 取指令等待周期*/
#define  IFMC_WAIT_1			IFMC_CR_WAIT		/* IFMC 取指令等待周期*/

#define  IFMC_CR_MODE       	         ((u32)0x00000100)         /* IFMC 操作模式 */
#define  IFMC_CR_AINC        	         ((u32)0x00002000)         /* IFMC 地址自动递增 */
#define  IFMC_CR_KEY_MAIN                ((u32)0xADEB0000)         /* IFMC主代码区擦写密码*/
#define  IFMC_CR_KEY_CONFIG              ((u32)0xC5AE000)          /* IFMC配置区区擦写密码*/
/*******************  Bit definition for IFMC_SR register  ******************/
#define  IFMC_SR_WOV                     ((u32)0x00000001)        /* 写操作完成 */
#define  IFMC_SR_POV                     ((u32)0x00000002)        /* 页擦除操作 */
#define  IFMC_SR_COV                     ((u32)0x00000004)        /* 全片擦除操作完成 */
#define  IFMC_SR_BUSY                    ((u32)0x00000008)        /* IFMC操作忙标志 */
#define  IFMC_SR_CERR                    ((u32)0x00000010)        /* IFMC操作错误标志 */
#define  IFMC_SR_KERR                    ((u32)0x00000020)        /* IFMC密码错误标志 */
#define  IFMC_SR_AERR                    ((u32)0x00000040)        /* IFMC地址错误标志 */
/*******************  Bit definition for IFMC_IE register  ******************/
#define  IFMC_IE_WOVI                   ((u32)0x00000001)        /* 写命令完成中断使能 */
#define  IFMC_IE_POVI                   ((u32)0x00000002)        /* 块擦除命令完成中断使能  */
#define  IFMC_IE_COVI                	((u32)0x00000004)        /* 全片擦除操作完成中断使能*/
#define  IFMC_IE_CERI                   ((u32)0x00000010)        /* IFMC操作命令错误中断使能 */
#define  IFMC_IE_KERI                   ((u32)0x00000020)        /* IFMC密码错误中断使能 */
#define  IFMC_IE_AERI                   ((u32)0x00000040)        /* IFMC地址错误中断使能 */
/*******************  Bit definition for IFMC_PSC register  *******************/
#define  IFMC_PSC_PSC                   ((u32)0x0000000F)        /* IFMC Address */
/********************  Bits definition for IFMC_BSR register  ******************/
#define IFMC_BSR_BSR                    ((u32)0x00000001)        /*  */
/********************  Bits definition for IFMC_RPT register  ******************/
#define IFMC_RPT_PSR                    ((u32)0x00000001)        /*  */
/********************  Bits definition for IFMC_IF register  ******************/
#define EXTI_IF_BIT0                        ((u16)0x0001)                 /*  外部中断标志位, bit 0 */
#define EXTI_IF_BIT1                        ((u16)0x0002)                 /*  外部中断标志位, bit 1 */
#define EXTI_IF_BIT2                        ((u16)0x0004)                 /*  外部中断标志位, bit 2 */
#define EXTI_IF_BIT3                        ((u16)0x0008)                 /*  外部中断标志位, bit 3 */
#define EXTI_IF_BIT4                        ((u16)0x0010)                 /*  外部中断标志位, bit 4 */
#define EXTI_IF_BIT5                        ((u16)0x0020)                 /*  外部中断标志位, bit 5 */
#define EXTI_IF_BIT6                        ((u16)0x0040)                 /*  外部中断标志位, bit 6 */
#define EXTI_IF_BIT7                        ((u16)0x0080)                 /*  外部中断标志位, bit 7 */
#define EXTI_IF_BIT8                        ((u16)0x0100)                 /*  外部中断标志位, bit 8 */
#define EXTI_IF_BIT9                        ((u16)0x0200)                 /*  外部中断标志位, bit 9 */
#define EXTI_IF_BIT10                       ((u16)0x0400)                 /*  外部中断标志位, bit 10*/
#define EXTI_IF_BIT11                       ((u16)0x0800)                 /*  外部中断标志位, bit 11*/
#define EXTI_IF_BIT12                       ((u16)0x1000)                 /*  外部中断标志位, bit 12*/
#define EXTI_IF_BIT13                       ((u16)0x2000)                 /*  外部中断标志位, bit 13*/
#define EXTI_IF_BIT14                       ((u16)0x4000)                 /*  外部中断标志位, bit 14*/
#define EXTI_IF_BIT15                       ((u16)0x8000)                 /*  外部中断标志位, bit 15*/

/******************************************************************************/
/*                                                                            */
/*      Universal Asynchronous Receiver Transmitter (UART)       */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for UART_DR register  *******************/
#define  UART_DR_DR                        ((u16)0x01FF)            /* DR[8:0] bits (Receiver Transmitter Buffer value) */
/******************  Bit definition for UART_CR register  *******************/
#define UART_CR_WP			((u32)0x00000007)        /* 数据帧与校验位配置 */
#define UART_WP_8D			((u32)0x00000001)
#define UART_WP_7D1P		((u32)0x00000003)
#define UART_WP_9D			((u32)0x00000004)
#define UART_WP_8D1P		((u32)0x00000007)

#define UART_CR_STOP		((u32)0x00000018)        /* STOP[1:0] bits (停止位长度选择) */
#define UART_STOP_05b		((u32)0x00000000)
#define UART_STOP_1b		((u32)0x00000008)
#define UART_STOP_15b		((u32)0x00000010)
#define UART_STOP_2b		((u32)0x00000018)

#define UART_CR_PS			((u32)0x00000020)        /* 奇偶校验方式 */
#define UART_PS_ODD			UART_CR_PS
#define UART_PS_EVEN		((u32)0x00000000)

#define  UART_CR_LPB        ((u32)0x00000040)        /* 回绕模式控制 */
#define  UART_CR_UE         ((u32)0x00000080)        /* 波特率发生器使能 */
#define  UART_CR_RE         ((u32)0x00000100)        /* 数据接收使能 */
#define  UART_RE_Enable		UART_CR_RE				 /* 数据接收使能 */
#define  UART_RE_Disable	((u32)0x00000000)		 /* 数据接收除能 */

#define  UART_CR_RXP		((u32)0x00010000)        /* 数据接收极性控制 */
#define  UART_CR_TXP		((u32)0x00020000)        /* 数据发送极性控制 */
#define  UART_CR_OWE		((u32)0x00200000)        /* OneWire模式使能 */

#define UART_CR_OWD		((u32)0x00400000)        /* OneWire模式收发方向控制 */
#define UART_OWD_TX		UART_CR_OWD
#define UART_OWD_RX		(~UART_CR_OWD)

/******************  Bit definition for UART_BRR register  *******************/
#define  UART_BRR_BR                      ((u32)0x0000FFFF)               /* BRR[15:0] bits (波特率配置) */
/******************  Bit definition for UART_IE register  *******************/
#define  UART_IE_RXNEI                     ((u32)0x00000001)        /* 接收缓冲队列非空中断允许控制位 */
#define  UART_IE_RXFI                      ((u32)0x00000004)        /* 接收缓冲队列全满中断允许控制位 */
#define  UART_IE_PEI                       ((u32)0x00000020)        /* 奇偶校验错误中断允许控制位 */
#define  UART_IE_FEI                       ((u32)0x00000040)        /* 帧错误中断允许控制位 */
#define  UART_IE_OVRI                      ((u32)0x00000080)        /* 接收缓冲队列溢出中断允许控制位 */
#define  UART_IE_TXEI                      ((u32)0x00000100)        /* 发送缓冲队列全空中断允许控制位 */
#define  UART_IE_TXFI                      ((u32)0x00000400)        /* 发送缓冲队列全满中断允许控制位 */
#define  UART_IE_TXOI                      ((u32)0x00000800)        /* 发送全部完成中断允许控制位 */
/******************  Bit definition for UART_SR register  *******************/
#define  UART_SR_RXNE                      ((u32)0x00000001)        /* 接收 FIFO 非空 */
#define  UART_SR_RXF                       ((u32)0x00000004)        /* 接收 FIFO 全满 */
#define  UART_SR_PE                        ((u32)0x00000020)        /* 校验错误 */
#define  UART_SR_FE                        ((u32)0x00000040)        /* 帧错误 */
#define  UART_SR_OVR                       ((u32)0x00000080)        /* 接收 FIFO 溢出错误 */
#define  UART_SR_TXE                       ((u32)0x00000100)        /* 发送 FIFO 为空 */
#define  UART_SR_TXF                       ((u32)0x00000400)        /* 发送 FIFO 全满 */
#define  UART_SR_TXO                       ((u32)0x00000800)        /* 发送数据完毕 */
/******************  Bit definition for UART_TXFR register  *******************/
#define  UART_TXFR_TXFR                    ((u32)0xFFFFFFFF)        /* TXFR[31:0] bits (发送FIFO复位) */
/******************  Bit definition for UART_RXFR register  *******************/
#define  UART_RXFR_RXFR                    ((u32)0xFFFFFFFF)        /* RXFR[31:0] bits (接收FIFO复位) */
/******************  Bit definition for UART_IRC register  *******************/
#define  UART_IRC_IRE                      ((u32)0x00000001)        /*红外功能使能控制 */
#define  UART_IRC_IRPN                     ((u32)0x00000002)        /*红外发送极性控制 */
#define  UART_IRC_IRBD                     ((u32)0x00000030)        /*IRC[1:0]红外速率选择控制 */

/******************  Bit definition for UART_IRDC register  *******************/
#define  UART_IRDC_DUTY                    ((u32)0x00000FFF)        /* IRDC[11:0] bits (红外调制占空比控制) */

/******************************************************************************/
/*                                                                            */
/*                      Analog to Digital Converter (ADC)                     */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for ADC_CR register  ******************/
#define ADC_CR_CHS                         ((u32)0x0000000F)        /* Channel 11 selection */
#define ADC_CR_CHS_10                      ((u32)0x0000000A)        /* Channel 10 selection */
#define ADC_CR_CHS_9                       ((u32)0x00000009)        /* Channel 9 selection  */
#define ADC_CR_CHS_8                       ((u32)0x00000008)        /* Channel 8 selection  */
#define ADC_CR_CHS_7                       ((u32)0x00000007)        /* Channel 7 selection  */
#define ADC_CR_CHS_6                       ((u32)0x00000006)        /* Channel 6 selection  */
#define ADC_CR_CHS_5                       ((u32)0x00000005)        /* Channel 5 selection  */
#define ADC_CR_CHS_4                       ((u32)0x00000004)        /* Channel 4 selection  */
#define ADC_CR_CHS_3                       ((u32)0x00000003)        /* Channel 3 selection  */
#define ADC_CR_CHS_2                       ((u32)0x00000002)        /* Channel 2 selection  */
#define ADC_CR_CHS_1                       ((u32)0x00000001)        /* Channel 1 selection  */
#define ADC_CR_CHS_0                       ((u32)0x00000000)        /* Channel 0 selection  */
#define ADC_CR_ADEN                        ((u32)0x00000020)        /* ADC enable control   */
#define ADC_CR_SOC                         ((u32)0x00000080)        /*                   */

#define ADC_CR_PSC				((u32)0x00000300)        /* CLKDIV[9:8] bits( )  */
#define ADC_CR_PSC_2			((u32)0x00000000)
#define ADC_CR_PSC_4			((u32)0x00000100)
#define ADC_CR_PSC_8			((u32)0x00000200)
#define ADC_CR_PSC_16			ADC_CR_PSC

#define ADC_CR_MODE			((u32)0x00001800)        /* ADC mode             */
#define ADC_CR_MODE_Single		((u32)0x00000000)	/*单次转换模式*/
#define ADC_CR_MODE_Target		((u32)0x00000800)	/*TIM 事件触发转换模式*/
#define ADC_CR_MODE_Continuous	((u32)0x00001000)	/*连续转换模式*/

#define ADC_CR_ALIGN			((u32)0x00002000)        /* Data Alignment */
#define ADC_ALIGN_Right			((u32)0x00000000)
#define ADC_ALIGN_Left			ADC_CR_ALIGN

#define ADC_CR_BGS				((u32)0x00004000)
#define ADC_BGS_BG1v2			((u32)0x00000000)
#define ADC_BGS_BG1v0			ADC_CR_BGS

#define ADC_CR_TIMS                        ((u32)0x000F0000)
#define ADC_CR_TIMS_TIM1_TRGO	((u32)0x00050000)
#define ADC_CR_TIMS_TIM1_OC1	((u32)0x00060000)
#define ADC_CR_TIMS_TIM1_OC2	((u32)0x00070000)
#define ADC_CR_TIMS_TIM1_OC3	((u32)0x00080000)
#define ADC_CR_TIMS_TIM1_OC4	((u32)0x00090000)
#define ADC_CR_TIMS_TIM2_TRGO	((u32)0x000A0000)
#define ADC_CR_TIMS_TIM3_TRGO	((u32)0x000B0000)
#define ADC_CR_TIMS_None		((u32)0x00000000)
/********************  Bits definition for ADC_SR register  ******************/
#define ADC_SR_EOC                         ((u32)0x00000001)       /* ADC End of Conversion */
#define ADC_SR_RDY                         ((u32)0x00000002)       /* ADC Ready */
/********************  Bit definition for ADC_DR register  ********************/
#define  ADC_DR_DATA                       ((u32)0x0000FFFF)        /* Regular data */
/********************  Bits definition for ADC_SAMPLE register  ******************/
#define ADC_SAMPLE_SMP                     ((u32)0x000000FF)       /*  */

/******************************************************************************/
/*                                                                            */
/*                   Inter-integrated Circuit Interface (I2C)                 */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for I2C_CR register  *******************/
#define I2C_CR_ACK                         ((u32)0x00000004)        /* ACK generation (slave mode) */
#define I2C_ACK_Enable			I2C_CR_ACK
#define I2C_ACK_Disable			((u32)0x00000000)

#define  I2C_CR_SI                          ((u32)0x00000008)        /* Interrupt status */
#define  I2C_CR_STOP                        ((u32)0x00000010)        /* STOP generation (master mode) */
#define  I2C_CR_STAR                        ((u32)0x00000020)        /* START generation */
#define  I2C_CR_PE                          ((u32)0x00000040)        /* Peripheral enable */
#define  I2C_CR_HCT                         ((u32)0x0000F000)        /* CLK filtering delay*/
#define  I2C_CR_BR                          ((u32)0x03FF0000)        /* CLK DIV*/
/*******************  Bit definition for I2C_SR register  *******************/
#define I2C_SR_SR                          ((u32)0x000000F8)
#define I2C_Stop 0x00				/* 总线上出现一个停止信号*/
#define I2C_StartOk 0x01			/* 起始信号发送完毕*/
#define I2C_ReStartOk 0x02		/* 重复起始信号发送完毕*/
#define I2C_MAS_GetAck_W 0x03	/* 主机， 地址字发送完毕， 收到 ACK*/
#define I2C_MAS_GetNack_W 0x04	/* 主机， 地址字发送完毕， 收到 NACK*/
#define I2C_MDS_GetAck 0x05		/* 主机， 数据字发送完毕， 收到 ACK*/
#define I2C_MDS_GetNack 0x06	/* 主机， 数据字发送完毕， 收到 NACK*/
#define I2C_MAL  0x07			/* 主机， 总线仲裁失败*/
#define I2C_MAS_SendAck_R 0x08	/* 主机， 地址字发送完毕， 回送 ACK*/
#define I2C_MAS_SendNack_R 0x09/* 主机， 地址字发送完毕， 回送 NACK*/
#define I2C_MDG_SendAck 0x0A	/* 主机， 数据字接收完毕， 回送 ACK*/
#define I2C_MDG_SendNack 0x0B	/* 主机， 数据字接收完毕， 回送 NACK*/

#define I2C_SAG_SendAck_W 0x0C		/* 从机， 地址字接收完毕， 回送 ACK*/
#define I2C_SAL_AG_SendAck_W 0x0D	/* 从机，总线仲裁失败转化的从机， 地址字接收完毕， 回送 ACK*/
#define I2C_SBCAG_SendAck 0x0E		/* 从机，广播地址字接收完毕， 回送 ACK*/
#define I2C_SAL_BCAG_SendAck 0x0F	/* 从机，总线仲裁失败转化的从机，广播地址字接收完毕， 回送 ACK*/
#define I2C_SDG_SendAck 0x10	/* 从机， 数据字接收完毕， 回送 ACK*/
#define I2C_SDG_SendNack 0x11	/* 从机， 数据字接收完毕， 回送 NACK*/
#define I2C_SBCDG_SendAck 0x12	/* 从机， 广播数据字接收完毕， 回送 ACK*/
#define I2C_SBCDG_SendNack 0x13/* 从机， 广播数据字接收完毕， 回送 NACK*/
#define I2C_SDG_GSRS 0x14		/* 从机， 数据字接收完毕， 接收到停止信号或重复起始信号*/
#define I2C_SAG_SendAck_R 0x15	/* 从机， 地址字接收完毕， 回送 ACK*/
#define I2C_SAL_AG_SendAck_R 0x16		/* 从机， 主机总线仲裁失败转化的从机,地址字接收完毕， 回送 ACK*/
#define I2C_SDS_ReadAck 0x17	/* 从机， 数据字发送完毕， 收到 ACK*/
#define I2C_SDS_ReadNack 0x18	/* 从机， 数据字发送完毕， 收到 NACK*/
#define I2C_SDSSA_GSRS 0x19		/* 从机， 数据字接收完毕， 回送 ACK 后、接收到停止信号或重复起始信号*/
#define I2C_IDLE 0x1f			/* 总线空闲*/

/*******************  Bit definition for I2C_DR register  *******************/
#define  I2C_DR_DR                          ((u32)0x000000FF)        /* Enable Broadcast addressing*/
/*******************  Bit definition for I2C_OAR register  *******************/
#define I2C_OAR_BC				((u32)0x00000001)        /* Enable Broadcast addressing  */
#define I2C_BC_Enable			I2C_OAR_BC
#define I2C_BC_Disable			((u32)0x00000000)

#define  I2C_OAR_ADDR                       ((u32)0x000000FE)        /* Enable Broadcast addressing  */
/*******************  Bit definition for I2C_CCR register  *******************/
#define  I2C_CCR_MASK                       ((u32)0x000000FF)        /*  */
#define  I2C_CCR_ACK                        ((u32)0x00000004)        /* ACK generation (slave mode) */
#define  I2C_CCR_SI                         ((u32)0x00000008)        /* Interrupt status */
#define  I2C_CCR_STOP                       ((u32)0x00000010)        /* STOP generation (master mode) */
#define  I2C_CCR_STAR                       ((u32)0x00000020)        /* START generation */
#define  I2C_CCR_PE                         ((u32)0x00000040)        /* Peripheral enable */
#define  I2C_CCR_HCT                        ((u32)0x0000F000)        /* CLK filtering delay*/
#define  I2C_CCR_BR                         ((u32)0x03FF0000)        /* CLK DIV*/

/******************************************************************************/
/*                                                                            */
/*                        Serial Peripheral Interface (SPI)                   */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for SPI_CR1 register  ********************/
#define  SPI_CR1_DFF                         ((u32)0x0000000F)         /* SPI_data_size */
#define  SPI_CR1_DFF_4b                      ((u32)0x00000003)         /* Data frame length is 4 bits  */
#define  SPI_CR1_DFF_5b                      ((u32)0x00000004)         /* Data frame length is 5 bits  */
#define  SPI_CR1_DFF_6b                      ((u32)0x00000005)         /* Data frame length is 6 bits  */
#define  SPI_CR1_DFF_7b                      ((u32)0x00000006)         /* Data frame length is 7 bits  */
#define  SPI_CR1_DFF_8b                      ((u32)0x00000007)         /* Data frame length is 8 bits  */
#define  SPI_CR1_DFF_9b                      ((u32)0x00000008)         /* Data frame length is 9 bits  */
#define  SPI_CR1_DFF_10b                     ((u32)0x00000009)         /* Data frame length is 10 bits  */
#define  SPI_CR1_DFF_11b                     ((u32)0x0000000A)         /* Data frame length is 11 bits  */
#define  SPI_CR1_DFF_12b                     ((u32)0x0000000B)         /* Data frame length is 12 bits  */
#define  SPI_CR1_DFF_13b                     ((u32)0x0000000C)         /* Data frame length is 13 bits  */
#define  SPI_CR1_DFF_14b                     ((u32)0x0000000D)         /* Data frame length is 14 bits  */
#define  SPI_CR1_DFF_15b                     ((u32)0x0000000E)         /* Data frame length is 15 bits  */
#define  SPI_CR1_DFF_16b                     ((u32)0x0000000F)         /* Data frame length is 16 bits  */

#define SPI_CR1_CPOL			((u32)0x00000040)         /* Clock Polarity */
#define SPI_CPOL_Low			((u16)0x0000)
#define SPI_CPOL_High			SPI_CR1_CPOL

#define  SPI_CR1_CPHA			((u32)0x00000080)         /* Clock Phase */
#define SPI_CPHA_1Edge			((u16)0x0000)
#define SPI_CPHA_2Edge			SPI_CR1_CPHA

#define  SPI_CR1_SCR                         ((u32)0x0000FF00)         /* Post-division factor */
/*******************  Bit definition for SPI_CR2 register  ********************/
#define  SPI_CR2_LBM				((u32)0x00000001)         /* Loopback Mode */
#define  SPI_CR2_SPE				((u32)0x00000002)         /* Loopback Mode */
#define  SPI_CR2_MSM			((u32)0x00000004)         /* Master-slave selection */
#define SPI_CR2_MSM_Master		((u16)0x0000)
#define SPI_CR2_MSM_Slave		((u16)0x0004)
/********************  Bit definition for SPI_DR register  ********************/
#define  SPI_DR_DR                           ((u16)0xFFFF)            /* Data Register */
/********************  Bit definition for SPI_SR1 register  ********************/
#define  SPI_SR1_TXE                         ((u32)0x00000001)         /* Transmission FIFO is empty */
#define  SPI_SR1_TNF                         ((u32)0x00000002)         /* Transmission FIFO is not empty */
#define  SPI_SR1_RXNE                        ((u32)0x00000004)         /* Receiver FIFO is not empty */
#define  SPI_SR1_RXF                         ((u32)0x00000008)         /* Receiver FIFO is Full */
#define  SPI_SR1_BSY                         ((u32)0x00000010)         /* Transmission module is busy */	//错误，由08改为10
/********************  Bit definition for SPI_BR register  ********************/
#define  SPI_BR_BR                           ((u32)0x000000FF)         /* Prescaler factor */
/********************  Bit definition for SPI_IE register  ********************/
#define  SPI_IE_OVRE                        ((u32)0x00000001)         /* Receiver FIFO overflow */
#define  SPI_IE_OTE                         ((u32)0x00000002)         /* Receiver FIFO Non-empty timeout */
#define  SPI_IE_RXHE                        ((u32)0x00000004)         /* Receiver FIFO Half-full */
#define  SPI_IE_TXHE                        ((u32)0x00000008)         /* Transmission FIFO Half-full */
/********************  Bit definition for SPI_SR2 register  ********************/
#define  SPI_SR2_VOR                        ((u32)0x00000001)         /* Receiver FIFO overflow */
#define  SPI_SR2_OT                         ((u32)0x00000002)         /* Receiver FIFO Non-empty timeout */
#define  SPI_SR2_RXH                        ((u32)0x00000004)         /* Receiver FIFO Half-full */
#define  SPI_SR2_TXH                        ((u32)0x00000008)         /* Transmission FIFO Half-full */
/********************  Bit definition for SPI_IFC register  ********************/
#define  SPI_IFC_OVR                       ((u32)0x00000001)         /* Receiver FIFO overflow */
#define  SPI_IFC_OT                         ((u32)0x00000002)         /* Receiver FIFO Non-empty timeout */
/********************  Bit definition for SPI_CSS register  ********************/
#define  SPI_CSS_CSS				((u32)0x00000004)         /* CS is controlled by software  */
#define SPI_CSS_Soft				SPI_CSS_CSS
#define SPI_CSS_Hard			((u16)0x0000)

#define  SPI_CSS_SWCS			((u16)0x0008)         /* CS Set Bit by software  */
#define SPI_SWCS_High			SPI_CSS_SWCS
#define SPI_SWCS_Low			((u16)0x0000)

/******************************************************************************/
/*                                                                            */
/*                      TIM1 Registers                                     */
/*                                                                            */
/******************************************************************************/

/*******************  Bit definition for TIM1_SR register  *******************/
#define  TIM1_SR_ARF                      ((u32)0x00000001)       /*定时器匹配0标志位      */
#define  TIM1_SR_OC1F                     ((u32)0x00000002)       /*定时器匹配1标志位      */
#define  TIM1_SR_OC2F                     ((u32)0x00000004)       /*定时器匹配2标志位      */
#define  TIM1_SR_OC3F                     ((u32)0x00000006)       /*定时器匹配3标志位      */
#define  TIM1_SR_OC4F                     ((u32)0x00000010)       /*定时器匹配4标志位      */
#define  TIM1_SR_IC1F                     ((u32)0x00000020)       /*定时器匹配1下降沿标志位 */
#define  TIM1_SR_IC1R                     ((u32)0x00000040)       /*定时器捕获1上升沿标志位 */
#define  TIM1_SR_IC2F                     ((u32)0x00000080)       /*定时器匹配2下降沿标志位 */
#define  TIM1_SR_IC2R                     ((u32)0x00000100)       /*定时器匹配2上升沿标志位 */
#define  TIM1_SR_IC3F                     ((u32)0x00000200)       /*定时器匹配3下降沿标志位 */
#define  TIM1_SR_IC3R                     ((u32)0x00000400)       /*定时器匹配3上升沿标志位 */
#define  TIM1_SR_IC4F                     ((u32)0x00000800)       /*定时器匹配4下降沿标志位 */
#define  TIM1_SR_IC4R                     ((u32)0x00001000)       /*定时器匹配4上升沿标志位 */
#define  TIM1_SR_BIF                      ((u32)0x00002000)       /*定时器刹车输入标志位    */
/*******************  Bit definition for TIM1_CR1 register  *******************/
#define  TIM1_CR1_CEN                     ((u32)0x00000001)       /*定时器使能控制位           */
#define  TIM1_CR1_UG                    	((u32)0x00000002)       /*定时器匹配值更新           */
#define  TIM1_CR1_CLKS                    ((u32)0x00000004)       /*定时器时钟选择控制         */

#define  TIM1_CR1_BKIS                    ((u32)0x00000070)       /*定时器刹车输入源选择控制位  */
#define  TIM1_CR1_BKIS_TIMx_BKIN          ((u32)0x00000000)
#define  TIM1_CR1_BKIS_PLLCLKDISABLE      ((u32)0x00000030)
#define  TIM1_CR1_BKIS_PVD                ((u32)0x00000060)
#define  TIM1_CR1_BKIS_SOFT               ((u32)0x00000070)

#define  TIM1_CR1_BKIC                    ((u32)0x00000080)       /*定时器刹车输入停止使能控制位*/
#define  TIM1_Break_Idle                    ((u32)0x00000000)
#define  TIM1_Break_Close                 TIM1_CR1_BKIC

#define  TIM1_CR1_DBGR                    ((u32)0x00000100)       /*定时器调试挂起控制位        */
/*******************  Bit definition for TIM1_ITARR register  *******************/
#define  TIM1_ITARR                       ((u8)0xF)               /*ITARR[3:0]定时器中断累计次数控制位   */
/*******************  Bit definition for TIM1_ITCNT register  *******************/
#define  TIM1_ITCNT                       ((u8)0xF)               /*ITCNT[3:0]定时器中断累计次数当前计数值   */
/*******************  Bit definition for TIM1_PSC register  *******************/
#define  TIM1_PSC                         ((u16)0xFFFF)            /*PR[7:0]定时器预分频系数   */
/*******************  Bit definition for TIM1_CNT register  *******************/
#define  TIM1_CNT                         ((u16)0xFFFF)           /*PC[15:0]定时器当前计数值   */
/*******************  Bit definition for TIM1_CR2 register  *******************/
#define  TIM1_CR2_ARI                     ((u32)0x00000001)       /*PMW_TC和TIM1_ARR匹配时产生中断控制位        */
#define  TIM1_CR2_OC1I                    ((u32)0x00000002)       /*PMW_TC和TIM1_OCR1匹配时产生中断控制位        */
#define  TIM1_CR2_OC2I                    ((u32)0x00000004)       /*PMW_TC和TIM1_OCR2匹配时产生中断控制位        */
#define  TIM1_CR2_OC3I                    ((u32)0x00000008)       /*PMW_TC和TIM1_OCR3匹配时产生中断控制位        */
#define  TIM1_CR2_OC4I                    ((u32)0x00000010)       /*PMW_TC和TIM1_OCR4匹配时产生中断控制位        */
#define  TIM1_CR2_OPM                     ((u32)0x00000020)       /*PMW_TC和TIM1_ARR匹配时计时器停止控制位      */
#define  TIM1_CR2_DIR                     ((u32)0x00000040)       /*TIM1_CNT计数方向控制位                       */
#define  TIM1_CR2_CMS                     ((u32)0x00000080)       /*TIM1_CNT计数方向交替控制位                   */
/*******************  Bit definition for TIM1_ARR register  *******************/
#define  TIM1_ARR                         ((u16)0xFFFF)            /*ARR [15:0]定时器MR0匹配值   */
/*******************  Bit definition for TIM1_OCR1 register  *******************/
#define  TIM1_OCR1                        ((u16)0xFFFF)            /*MR1[15:0]定时器MR1匹配值   */
/*******************  Bit definition for TIM1_OCR2 register  *******************/
#define  TIM1_OCR2                        ((u16)0xFFFF)            /*MR2[15:0]定时器MR2匹配值   */
/*******************  Bit definition for TIM1_OCR3 register  *******************/
#define  TIM1_OCR3                        ((u16)0xFFFF)            /*MR3[15:0]定时器MR3匹配值   */
/*******************  Bit definition for TIM1_OCR4 register  *******************/
#define  TIM1_OCR4                        ((u16)0xFFFF)            /*MR4[15:0]定时器MR4匹配值   */
/*******************  Bit definition for TIM1_CAPR register  *******************/
#define  TIM1_CAPR_IC1R                   ((u32)0x00000001)       /*通道1脉冲上升沿捕捉使能控制          */
#define  TIM1_CAPR_IC1F                   ((u32)0x00000002)       /*通道1脉冲下降沿捕捉使能控制          */
#define  TIM1_CAPR_IC1RC                  ((u32)0x00000004)       /*通道1脉冲沿捕捉计数器复位使能控制    */
#define  TIM1_CAPR_IC1I                   ((u32)0x00000008)       /*通道1脉冲沿捕捉中断使能控制          */
#define  TIM1_CAPR_IC2R                   ((u32)0x00000010)       /*通道2脉冲上升沿捕捉使能控制          */
#define  TIM1_CAPR_IC2F                   ((u32)0x00000020)       /*通道2脉冲下降沿捕捉使能控制          */
#define  TIM1_CAPR_IC2RC                  ((u32)0x00000040)       /*通道2脉冲沿捕捉计数器复位使能控制    */
#define  TIM1_CAPR_IC2I                   ((u32)0x00000080)       /*通道2脉冲沿捕捉中断使能控制          */
#define  TIM1_CAPR_IC3R                   ((u32)0x00000100)       /*通道3脉冲上升沿捕捉使能控制          */
#define  TIM1_CAPR_IC3F                   ((u32)0x00000200)       /*通道3脉冲下降沿捕捉使能控制          */
#define  TIM1_CAPR_IC3RC                  ((u32)0x00000400)       /*通道3脉冲沿捕捉计数器复位使能控制    */
#define  TIM1_CAPR_IC3I                   ((u32)0x00000800)       /*通道3脉冲沿捕捉中断使能控制          */
#define  TIM1_CAPR_IC4R                   ((u32)0x00001000)       /*通道4脉冲上升沿捕捉使能控制          */
#define  TIM1_CAPR_IC4F                   ((u32)0x00002000)       /*通道4脉冲下降沿捕捉使能控制          */
#define  TIM1_CAPR_IC4RC                  ((u32)0x00004000)       /*通道4脉冲沿捕捉计数器复位使能控制    */
#define  TIM1_CAPR_IC4I                   ((u32)0x00008000)       /*通道4脉冲沿捕捉中断使能控制          */
/*******************  Bit definition for TIM1_ICR1 register  *******************/
#define  TIM1_ICR1_ICR1                   ((u32)0x0000FFFF)       /*CAP[15:0]捕捉通道1沿变化计数值   */
/*******************  Bit definition for TIM1_ICR2 register  *******************/
#define  TIM1_ICR2_ICR2                   ((u32)0x0000FFFF)       /*CAP[15:0]捕捉通道2沿变化计数值   */
/*******************  Bit definition for TIM1_ICR3 register  *******************/
#define  TIM1_ICR3_ICR3                   ((u32)0x0000FFFF)       /*CAP[15:0]捕捉通道3沿变化计数值   */
/*******************  Bit definition for TIM1_ICR4 register  *******************/
#define  TIM1_ICR4_ICR4                   ((u32)0x0000FFFF)       /*CAP[15:0]捕捉通道4沿变化计数值   */
/*******************  Bit definition for TIM1_OCMR register  *******************/
#define  TIM1_OCMR_OC1M                   ((u32)0x00000003)       /*MC1[2:0]  输出通道1比较输出模式选择    */
#define  TIM1_OCMR_OC1P                   ((u32)0x00000004)       /*输出通道1极性选择                      */
#define  TIM1_OCMR_OC1NP                  ((u32)0x00000008)       /*输出通道1互补输出极性选择              */
#define  TIM1_OCMR_OC2M                   ((u32)0x00000030)       /*MC2[6:4]  输出通道2比较输出模式选择    */
#define  TIM1_OCMR_OC2P                   ((u32)0x00000040)       /*输出通道2极性选择                      */
#define  TIM1_OCMR_OC2NP                  ((u32)0x00000080)       /*输出通道2互补输出极性选择              */
#define  TIM1_OCMR_OC3M                   ((u32)0x00000300)       /*MC3[10:8] 输出通道3比较输出模式选择    */
#define  TIM1_OCMR_OC3P                   ((u32)0x00000400)       /*输出通道3极性选择                      */
#define  TIM1_OCMR_OC3NP                  ((u32)0x00000800)       /*输出通道3互补输出极性选择              */
#define  TIM1_OCMR_OC4M                   ((u32)0x00003000)       /*MC4[14:12]输出通道4比较输出模式选择    */
#define  TIM1_OCMR_OC4P                   ((u32)0x00004000)       /*输出通道4极性选择                      */
#define  TIM1_OCMR_OC4NP                  ((u32)0x00008000)       /*输出通道4互补输出极性选择              */
#define  TIM1_OCMR_OIS1                   ((u32)0x00010000)       /*输出通道1初始值                        */
#define  TIM1_OCMR_OIS2                   ((u32)0x00020000)       /*输出通道2初始值                        */
#define  TIM1_OCMR_OIS3                   ((u32)0x00040000)       /*输出通道3初始值                        */
#define  TIM1_OCMR_OIS4                   ((u32)0x00080000)       /*输出通道4初始值                        */
#define  TIM1_OCMR_OIS1N                  ((u32)0x00100000)       /*输出通道1初始值                        */
#define  TIM1_OCMR_OIS2N                  ((u32)0x00200000)       /*输出通道2初始值                        */
#define  TIM1_OCMR_OIS3N                  ((u32)0x00400000)       /*输出通道3初始值                        */
#define  TIM1_OCMR_OIS4N                  ((u32)0x00800000)       /*输出通道4初始值                        */
#define  TIM1_OCMR_OC1NE                  ((u32)0x01000000)       /*输出通道1互补输出使能                  */
#define  TIM1_OCMR_OC2NE                  ((u32)0x02000000)       /*输出通道2互补输出使能                  */
#define  TIM1_OCMR_OC3NE                  ((u32)0x04000000)       /*输出通道3互补输出使能                  */
#define  TIM1_OCMR_OC4NE                  ((u32)0x08000000)       /*输出通道4互补输出使能                  */
#define  TIM1_OCMR_BKE                    ((u32)0x10000000)       /*刹车输入使能控制                       */
#define  TIM1_Break_Enable               TIM1_OCMR_BKE
#define  TIM1_Break_Disable              ((u32)0x00000000)

#define  TIM1_OCMR_BKP				((u32)0x20000000)       /*刹车输入有效电平控制                   */
#define TIM1_BreakPolarity_High		TIM1_OCMR_BKP
#define TIM1_BreakPolarity_Low		((u32)0x00000000)

#define  TIM1_OCMR_BKI                    ((u32)0x40000000)       /*刹车输入中断使能控制                   */
#define  TIM1_OCMR_SWBK                   ((u32)0x80000000)       /*软件刹车输入                           */
/*******************  Bit definition for TIM1_DT register  *******************/
#define  TIM1_DT                          ((u8)0xFF)              /*DT[7:0]死区时间控制   */

/******************************************************************************/
/*                                                                            */
/*                      TIMx Registers                                     */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for TIMx_SR register  *******************/
#define  TIMx_SR_ARF                     ((u32)0x00000001)        /*定时器与TIMx_ARR值匹配中断标志位       */
/*******************  Bit definition for TIMx_CR1 register  *******************/
#define  TIMx_CR1_CEN                    ((u32)0x00000001)        /*定时器使能控制位        */
#define  TIMx_CR1_UG                    ((u32)0x00000002)        /*定时器匹配值更新        */
#define  TIMx_CR1_DBGR                   ((u32)0x00000100)        /*定时器调试挂起控制位    */
/*******************  Bit definition for TIMx_PSC register  *******************/
#define  TIMx_PSC                        ((u16)0xFFFF)            /*TIMx_PSC[16:0]定时器预分频系数   */
/*******************  Bit definition for TIMx_CNT register  *******************/
#define  TIMx_CNT                        ((u16)0xFFFF)            /*PC[15:0]定时器当前计数值   */
/*******************  Bit definition for TIMx_CR2 register  *******************/
#define  TIMx_CR2_ARI                    ((u32)0x00000001)        /*TIMx_CNT与TIMx_ARR值匹配时产生中断控制位          */
#define  TIMx_CR2_RSTC                   ((u32)0x00000002)        /*TIMx_CNT与TIMx_ARR值匹配时计数复位控制位          */
#define  TIMx_CR2_OPM                   ((u32)0x00000004)        /*TIMx_CNT与TIMx_ARR值匹配时计数器停止控制位        */
#define  TIMx_CR2_DIR                    ((u32)0x00000008)        /*TIMx_CNT计数方向控制位                       */
/*******************  Bit definition for TIMx_ARR register  *******************/
#define  TIMx_ARR                        ((u16)0xFFFF)            /*TIMx_ARR[15:0]定时器MR0匹配值   */


/******************************************************************************/
/*                                                                            */
/*                      CRC Registers                                     */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for CRC_CR register  *******************/
#define CRC_CR_CEN		((u32)0x00000001)	/* CRC Enable */
#define CRC_CR_CRS		((u32)0x00000002)	/* CRC Initial */
#define CRC_CR_CIS		((u32)0x00000004)	/* CRC DataIn Width */
#define CRC_CIS_16b		CRC_CR_CIS			/* CRC DataIn Width 16bit*/
#define CRC_CIS_8b		((u32)0x00000000)	/* CRC DataIn Width 8bit*/

#define CRC_CR_CISN                         ((u32)0x00000008)          /* CRC DataIn Width */
#define CRC_CR_CBN                          ((u32)0x00000010)          /* CRC DataIn Width */
#define CRC_CR_COSN                         ((u32)0x00000020)          /* CRC DataIn Width */
/*******************  Bit definition for CRC_SEED register  *******************/
#define CRC_SEED_MASK                       ((u32)0x0000FFFF)          /* CRC SEED */
/*******************  Bit definition for CRC_POLY register  *******************/
#define CRC_POLY_MASK                       ((u32)0x0000FFFF)          /* CRC SEED */
/*******************  Bit definition for CRC_POLY register  *******************/
#define CRC_DIN_MASK                        ((u32)0x0000FFFF)           /* CRC DATA INPUT */
/*******************  Bit definition for CRC_POLY register  *******************/
#define CRC_DOUT_MASK                       ((u32)0x0000FFFF)          /* CRC DATA OUT */

/******************************************************************************/
/*                                                                            */
/*                        Independent WATCHDOG (IWDG)                         */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for IWDG_RLR register  *******************/
#define  IWDG_RLR_RL                        ((u32)0xFFFFFFFF)            /* Watchdog counter reload value */
/*******************  Bit definition for IWDG_CR register  *******************/
#define  IWDG_CR_EN                         ((u32)0x00000001)            /* Enable IWDG        */
#define  IWDG_CR_RSTE                       ((u32)0x00000002)            /* RESET IWDG         */
#define  IWDG_CR_DBGE                       ((u32)0x00000004)            /* RESET IWDG         */
/*******************  Bit definition for IWDG_RIS register  *******************/
#define  IWDG_SR_HDF                       ((u32)0x00000001)            /* Watchdog counter reload value update */
/*******************  Bit definition for IWDG_KR register  ********************/
#define IWDG_LOCK_Status		((u32)0x00000001)            /* IWDG LOCK Status*/
#define WDG_LOCK_UnLock		((u32)0x1ACCE551)
#define WDG_LOCK_Lock			((u32)0x00000000)
/**
  * @}
  */


#ifdef USE_STDPERIPH_DRIVER
  #include "PT32X005_conf.h"
#endif


#ifdef __cplusplus
}
#endif

#endif



